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3-51 features 32 bidirectional cmos "t" switches in an 8 4 non-blocking array break-before-make switching con?uration fast setup & hold times for switch programming 3db bandwidth of 200mhz low feedthrough and crosstalk, better than -80db at 5mhz very low differential gain and phase errors 12vpp bipolar signal capability on-state resistance 75 ? (max) for v dd =+5v, v ee =-7v switch control through 2-stage latches orthogonal xi and yi pin connections for optimized pcb layout latch readback capability for monitoring applications high-end video routing and switching medical instrumentation automatic test equipment (ate) multi-media communication description the MT88V32 is a digitally programmable (ttl levels) 8 4 crosspoint switch that is designed to control wide-band analog (video) signal. each of the 32 nodes of the switching matrix has a t- switch, see fig.1. this grounds the nodes of all open connections, which greatly reduces feedthrough noise. in order to reduce crosstalk, individual analog signal lines are isolated by interleaving them with ground lines. the two stage programmable latch system allows the state of all switching nodes to be updated simultaneously. the next state of the switch is written into the ?st stage of the latches through individual write cycles. these changes will not affect the current state of the switch. the str obe2 control input is used to load the state of all ?st stage latches to the second stage latches, which updates the complete matrix. therefore, all 32 switching nodes are updated simultaneously. the MT88V32 supports separate analog (v ee ) and digital (v dd ) voltage references. this allows the user to select an optimum analog signal bias point. ordering information MT88V32ap 44 pin plcc -40 to 85 c figure 1 - functional block diagram y0-y7 vdd vss x0 gnd mr strobe2 strobe1 ax0-ax1 8x4 "t" switch array vee 2nd stage latches 1st stage latches address decode ay0-ay2 i/o logic control x1 x2 x3 r/w data cs yi xi gnd t-switch configuration issue 1 august 1993 MT88V32 8 x 4 high performance video switch array preliminary information
MT88V32 preliminary information 3-52 figure 2 - pin connections pin description pin #* name description 1, 3, 4, 6, 8, 10, 12, 14, 16, 18, 20, 39, 41, 43 gnd analog ground. connect to system ground for crosstalk noise isolation. pins 3 and 39 are not bonded internally. 2, 44, 42, 40 x0, x1, x2, x3 analog lines (input/output) . 5, 7, 9, 11, 13, 15, 17, 19 y0, y1, y2, y3 y4, y5, y6, y7 analog lines (input/output) . 21 v ee negative analog power supply. 22 ic internal connection. 23 v dd positive power supply. 24 v ss digital ground reference. 25, 26 ax1,ax0 x0-x3 i/o address select (inputs). 27, 30,31 ay2-ay0 y0-y7 i/o address select (inputs). 28, 29 nc no connection. 3 2 data data (input/output) . when input, a logic high will close the selected switch and a logic low will open the selected switch. when output, a logic high indicates a closed switch and a logic low indicates an opened switch. 33 cs chip select (input). active low. 34 r/w read/write control (input). when high the data pin is an output (for reading from second stage latch); when low the data pin is an input (for writing to ?st stage latch). 35 str obe1 strobe 1 (input). modi?s memory content of ?st stage latch as determined by the addess and data lines, but does not change the switch array con?uration of entire switch array. active low. 36 str obe2 strobe 2 (input). transfers memory content of ?st stage latch to the second stage latch and hence, changes the con?uration of entire switch array. active low. 37 mr master reset (input). used to reset the ?st and second stage latches. active low. 38 nc no connection. y1 gnd y2 gnd y3 gnd y4 gnd y5 gnd y6 gnd y7 gnd vee ic* vss ax1 ax0 ay2 nc vdd 1 65432 44434241 40 7 8 9 10 11 12 13 14 15 16 39 38 37 36 35 34 33 32 31 30 23 18 19 20 21 22 24 25 26 27 28 17 29 gnd nc mr str obe2 str obe1 r/w cs data ay0 ay1 nc x3 gnd x2 gnd x1 gnd x0 gnd gnd y0 gnd * connects tov ee
preliminary information MT88V32 3-53 functional description the state of the MT88V32 8 x 4 switching matrix is updated through a simple parallel processor interface. this interface provides access to 32 two stage latches, which determines the state (open/ close) of each switching array node. each latch (or node) is addressed by the ax0-ax1 and ay0-ay2 inputs as per table 2, and the data input will determine if the connection is to be made (data=1) or opened (data=0). the second stage of the two stage latches controls the current state of each switching node. the value held in the ?st stage is the input to the second stage. this allows the device to be programmed in two ways. that is, individual switching nodes may be updated one at a time, or all nodes may be updated at once. to update one node at a time the strobe2 input should be held low. this makes the second stage latches transparent and the matrix immediately re?cts the state of the ?st stage latches. a write cycle example follows: 1) strobe2 is low, 2) cs and r/w are low, mr is high, 3) ax0-ax1 and ay0-ay2 as per table 2, 4) data input high to close or low to open, and 5) strobe1 toggled from high-to-low-to-high. these steps (one write cycle) may be repeated for each switch state change. this can also be accomplished by holding str obe1 low and toggling str obe2 . see figure 14 for timing. to update all nodes simultaneously all switch state changes must be written into the ?st stage latches. this is accomplished by holding str obe2 high and performing steps 2) through 5) above for each switching node that is to be changed. writing to the ?st stage latches only will not affect the switching state of the matrix. when the changes have been made all the switches of the matrix may be updated simultaneously by toggling the str obe2 input from high-to-low-to high. when str obe2 is used to update the state of the MT88V32 all switch ?reaks are completed before any switch ?akes occur. there is approximately 10ns delay between ?reaks and ?akes? both the ?st and second stage latches will be cleared when the master reset (mr ) is taken from high-to-low. this will open all the switch nodes. the operation of mr is independent of cs , ax0-ax1, ay0-ay2 and r/w . the status of each switching array node (second stage latch) can be read through the bidirectional data pin. a read cycle example follows: 1) cs is low, r/w and mr are high, 2) ax0-ax1 and ay0-ay2 as per table 2, and 3) data output high for closed or low for open. note: x = don? care, 0 = logic "0" state, 1 = logic "1" state a logic 1 on data input closes a connection. a logic 0 on data input opens a connection. mr r/w cs data strobe1 strobe2 data 1 1 0 0 1 0 0 1 1 0 1 0 1 1 no change to 1st stage latch. 1st stage latch is loaded with data. 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1st stage latch is transparent. selected latch is cleared and set again (i.e., output follows input). 1 1 0 0 0 x 1 x 0 1 1 1 1 0 1st stage latch output is frozen. output of 1st stage latch is transferred to output of 2nd stage latches. 1 1 0 0 x 0 x x 1 0 0 1 0 2nd stage latch output is frozen. both 1st stage and 2nd stage latches are transparent. 1 0 1 1 0 1 0 1 x 1 x 1 data becomes an output and re?cts the contents of the 2nd stage latch addressed by ax0-ax1 and ay0-ay2. all crosspoints opened (data in 1st and 2nd stage latches are cleared). table 1 - truth tables
MT88V32 preliminary information 3-54 it should be noted that the str obe1 function is disabled during a read cycle. see fig. 15 for timing. the MT88V32 can operate from a dual rail power supply (v dd and v ee ) or a single rail power supply (v ss =v ee =0v) as per the recommended operating conditions. for minimum on-state resistance the supply voltages should be v dd =5.0 v dc , v ss =0 v dc and v ee =-7 v dc . the analog input signal should be biased at -2.0 v dc to achieve minimum differential phase and gain error (see ac electrical characteristics - crosspoint performance). applications figure 3 illustrates examples of how to connect the signal lines of the MT88V32 to various interfaces. input buffers allow the incoming signals to be scaled and biased to the optimum operating range of the MT88V32 (i.e., differential phase error, differential gain error and r on ). buffers will also allow a more precise input impedance to be implemented. for low grade video applications, signal lines may be connected directly, as long as the ultimate source and terminating impedances are matched. output buffers may be used to provide signal gain and impedance matching for external connections. additionally, they may be used to isolate parasitic device capacitance in multiple stage switching applications where high frequency roll-off is critical. crosstalk, as well as differential phase and gain error can be minimized by designing a low source impedance (e.g., 10 ohms), and a high terminating impedance (e.g., 10k) at each stage. if successive switching stages are not buffered, then a resistor to ground (r) should be present between the switches. selection of r is based on the following compromise: 1) as r is decreased to approach the source and terminating resistance values signal loss will increase and crosstalk will decrease, and 2) as r increases signal loss will decrease and crosstalk will increase. it is recommended that the power supply rails of the MT88V32 be decoupled with 0.1 f ceramic z5u and 10 f dipped tantalum capacitors. these capacitors should be as close to the device as possible. the signal pins of the MT88V32 are interleaved with analog ground lines. this allows the circuit designer to run ground tracks on both sides of each signal line to improve crosstalk immunity. the 8x4 bidirectional cmos t-switch con?uration is a modular switching element in a convenient package size. the inherent ?xibility of this device permits the designer to build large switching matrices, see analog switch application notes. a 5 a 4 a 3 a 2 a 1 a 0 d 0 function 0 0 0 1 0 1 0 1 0 1 0 1 1/0 1/0 y0 to x0 y7 to x3 1xxxx0 x mr 1xxxx1 x stb2 table 3 - address decoding for the processor interfaces note: x = unde?ed, 1/0 -1 = make, 0 = break ax1 ax0 ay2 ay1 ay0 switch connections 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 y0 to x0 y1 to x0 y2 to x0 y3 to x0 y4 to x0 y5 to x0 y6 to x0 y7 to x0 0 0 1 1 0 1 0 1 0 1 y0 to x1 y7 to x1 1 1 0 0 0 1 0 1 0 1 y0 to x2 y7 to x2 1 1 1 1 0 1 0 1 0 1 y0 to x3 y7 to x3 table 2 - address decode truth table
preliminary information MT88V32 3-55 figures 4, 5 and 6 show methods of interfacing the MT88V32 to motorola and intel microcontrollers. the address decoding for these con?urations is in table 3. video signal terminology 1) component video - separate red (r), blue (b), green (g), and synchronization signals. 2) composite video - contains luminance (brightness), chrominance (colour), and synchronization signal components in a single waveform. 3) synchronization signal - horizontal sync pulses are negative going excursions of the composite video signal that occur every 63.5 sec. their function is to align the horizontal sweep. vertical synchronization is achieved during the vertical blanking interval, which is about 1200 sec or 20 horizontal scan intervals long. it consists of a number of vertical synchronization and equalization pulses. 4) luminance - is the black to white brightness component of a composite video signal. its range is from reference white (maximum amplitude) to reference black (minimum amplitude). 5) chrominance - rides on the luminance signal and determines the hue (phase) and brightness (amplitude) of the colour component of a composite video signal. 6) colour burst - is about 9 (minimum 8) cycles of a 3.578545 mhz reference signal, which is transmitted with every horizontal sweep of the composite video signal. a phase comparison figure 3 - high frequency switching applications 75 ? 75 ? 75 ? wideband input buffers x0 x1 x2 x3 y0 y1 y2 y3 y4 y5 y6 y7 MT88V32 control interface 10k ? 10k ? 10k ? wideband output buffers 75 ? 75 ? 75 ? 10k ? 10k ? 10k ? wideband output buffers r to next switching stage
MT88V32 preliminary information 3-56 figure 4 - motorola non-multiplexed processor interface figure 5 - motorola multiplexed processor interface mc6800/ 6802/6809 2 vma a 5 -a 15 a 0 -a 4 d0 r/w MT88V32 stb1 stb2 mr cs ay0-ay1 ax0-ax2 data r/w 5 11 a0 a5 + a0 + vma a5 + a0 + vma a5 +vma notes: for the mc6802 2 will be e. for the mc6809 2 will be e and vma will be the or?d product of q and e. mc6801/ 6803/68hc11 (pc) ad 0 -ad 4 (pc) ad 5 -ad 7 (pb) a 8 -a 15 as e r/w MT88V32 data ay 0 ay 1 ay 2 ax0 ax1 cs stb2 mr stb1 r/w 3 74hct574 d 1 q 1 d 2 q 2 d 3 q 3 d 4 q 4 d 5 q 5 d 6 q 6 d 7 q 7 d 8 q 8 clk oc a5 + a0 a5 a5 + a0 5 ad0 8 ad0
preliminary information MT88V32 3-57 figure 6 - intel processor interface figure 7 - typical on-state resistance (r on ) vs. dc bias (vdc) @ v dd =+5v, v ee =-7v 8031/8051 8085 (p0) ad 0 -ad 4 (p0) ad 5 -ad 7 (p2) a 8 -a 15 ale wr rd MT88V32 data ay 0 ay 1 ay 2 ax0 ax1 cs stb2 mr stb1 r/w 3 74hct574 d 1 q 1 d 2 q 2 d 3 q 3 d 4 q 4 d 5 q 5 d 6 q 6 d 7 q 7 d 8 q 8 clk oc a5 + a0 a5 a5 + a0 5 ad0 8 ad0
MT88V32 preliminary information 3-58 figure 8 - single channel feedthrough (all crosspoints open) figure 9 - single channel crosstalk (one crosspoint closed) figure 10 - all channel crosstalk (all crosspoints closed)
preliminary information MT88V32 3-59 between this reference signal and the chrominance signal determines colour hue. 7) differential phase error - (measured in degrees) is a phase change in the chrominance signal due to a change in luminance amplitude. 8) differential gain error - (measured in percentage) is a change in amplitude of the chrominance signal due to a change in luminance amplitude. figure 11 - 3db frequency response
MT88V32 preliminary information 3-60 figure 12 - typical differential phase vs. ramp voltage figure 13 - typical differential gain vs. ramp voltage
preliminary information MT88V32 3-61 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? dc electrical characteristics are over recommended temperature range & recommended power supply voltages. typical ?ures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. ? dc electrical characteristics are over recommended temperature range & recommended power supply voltages. typical ?ures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. absolute maximum ratings * - voltages are with respect to v ss unless otherwise stated. parameter symbol min max units 1 supply voltage v dd to v ss v dd to v ee v ss to v ee gnd to v ss -0.3 -0.3 -0.3 v ee -0.3 15 15 15 v dd +0.3 v v v v 2 analog input voltage v in v ee -0.3 v dd +0.3 v 3 digital input voltage v ind v ss -0.3 v dd +0.3 v 4 continuous current (any analog i/o terminal) 15 ma 5 storage temperature -65 +150 c 6 operating temperature -40 +85 c 7 package power dissipation 600 mw recommended operating conditions - voltages are with respect to 0v unless otherwise stated. characteristics sym min typ max units test conditions 1 supply voltage v dd -v ee v ee -v ss v dd v ee 4.5 -8.5 4.5 -8.5 12 5.0 -7.0 13.2 0 13.2 0 v v v v v ee =v ss =0v v dd =4.5v, v ss =0v 2 analog input voltage v in v ee v dd v 3 digital input voltage v ind v ss v dd v 4 analog ground gnd v ee 0v dd v dc electrical characteristics ? - analog switch characteristics voltages are with respect to v dd =+5v, v ee =-7v, v ss =0v unless otherwise stated. 25 c85 c test characteristics sym typ max max units conditions 1 on-state resistance v ee =-7v v ee =-5v v ee =0v r on 50 60 140 65 75 185 75 85 220 ? ? ? v in =v dc =(v dd +v ee )/2 iv xi -v yj i = 0.4v see figure 7. 2 difference in on-state resistance between switches ? r on 61010 ? iv xi -v yj i = 0.4v v in =v dc =(v dd +v ee )/2 3 off-state leakage current i off 10 200 na v in =v dd or v ee 4 on-state leakage current i on 10 200 na v in =v dd or v ee dc electrical characteristics ? - power supplies - voltages are with respect to v dd =+5v, v ee =-7v, v ss =0v, mr = 0.8v unless otherwise stated. characteristics sym min typ max units test conditions 1 positive supply current i dd 1 0.4 5 100 1.5 15 a ma ma v ind =v dd or v ss v ind =2.4v v dd =12v, v ss =v ee =0v, v ind =3.4v 2 negative supply current i ee 1 1 1 100 100 100 a a a v ind =v dd or v ss v ind =2.4v v dd =12v, v ss =v ee =0v, v ind =3.4v
MT88V32 preliminary information 3-62 ? dc electrical characteristics are over recommended temperature range and recommended power supply voltages. typical ?ures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. algebraic convention is adopted in this data sheet where the most negative value is a minimum and the most positive value is a maximum. ? timing is over recommended temperature range. typical ?ures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. notes: ? ? valid for v ee =-7v, v dd =+5v and v dc =-2.0v. error will increase slightly if input is biased differently. input test signal: 700mv ramp biased @ -2.0vdc with a superimposed video signal of 285vrms @ 3.58 mhz. ? ? guaranteed by design and characterization and not subject to production testing. dc electrical characteristics ? - digital input/output voltages are with respect to v dd =5v, v ee =-7v, v ss =0v, unless otherwise stated. characteristics sym min typ max units test conditions 1 input logic "1" level v ih 2v v ih 3.3 v v ee =v ss =0, v dd =12v 2 input logic "0" level v il 0.8 v v il 0.8 v v ee =v ss =0, v dd =12v 3 input leakage (digital pins) i leak 1 10 av ind =v dd or v ss 4 data output high voltage v oh 2.4 v dd vi oh =7ma@v oh =2.4v 5 data output high current i oh 7 20 ma source v oh =2.4v 6 data output low voltage v ol v ss 0.4 v i ol =2ma@v ol =0.4v 7 data output low current i ol 2 5 ma sink v ol =0.4v 8 data high impedance leakage i oz 110 av o =0 to v dd ac electrical characteristics ? - crosspoint performance - voltages are with respect to v dd =+5v, v dc =0, v ee =-7v, v ss =0v, unlesss otherwise stated. also applicable for v ee =v ss =0, v dd =+12v, v dc =(v dd +v ee )/2. characteristics sym min typ max units test conditions 1 on-state xi capacitance ? ? c xi (on) 56 pf 1 xi to 1 yi 2 on-state yi capacitance ? ? c yi (on) 56 pf 1 yi to 1 xi 3 off-state xi capacitance ? ? c xi (off) 30 pf 4 off-state yi capacitance ? ? c yi (off) 15 pf 5 break-before-make interval t open 10 ns 6 single channel feedthrough (all crosspoints open) (see fig. 8) fdt -80 -62 db db r s = r l =75 ? v in =0.6vpp @ 5mhz v in =0.6vpp @ 15mhz 7 single channel feedthrough (all crosspoints closed) (see fig. 9) x talk (sc) -85 -68 db db r in = 10 ?, r l = 10k ? v in =0.6vpp @ 5mhz v in =0.6vpp @ 15mhz x talk (sc) -70 -50 db db r in = 75 ?, r l = 10k ? v in =0.6vpp @ 5mhz v in =0.6vpp @ 15mhz 8 all channel crosstalk (all crosspoints closed) (see fig. 10) x talk (ac) -55 db r in = 10 ?, r l = 10k ? v in =0.6vpp @ 5mhz 9 frequency response (see fig.11) f 3db 200 mhz r s = r l =50 ? 10 differential phase error dp 0.05 o see note ? ? , r s = 50 ?, r l = 75 ? 11 differential gain error dg 0.11 % see note ? ? , r s = 50 ?, r l = 75 ?
preliminary information MT88V32 3-63 ? timing is over recommended temperature range with v ih =5v, v il =0v, v oh =2.4v, v ol =0.8v, r l =3k ? (data) and r l =1k ? (analog). typical ?ures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. ac electrical characteristics ? - timing characteristics - voltages are with respect to v dd =+5v, v ee =-7v, v ss =0v, r l =1k ? , c l =50pf unlesss otherwise stated. also applicable for v ee =v ss =0, v dd =+12v. characteristics sym min typ max units test conditions 1 data to str obe1 setup t ds1 20 ns t dh1 = 20ns min. 2 data to str obe1 hold t dh1 10 ns t ds1 = 30ns min. 3cs to str obe1 setup t css1 20 ns 4cs to str obe1 hold t csh1 20 ns 5 address to str obe1 setup t ass1 20 ns 6 address to str obe1 hold t ash1 20 ns 7 str obe1 pulse width t spw1 75 ns 8 str obe2 pulse width t spw2 75 ns 9 r/w to str obe1 setup t rwss1 20 ns 10 r/w to str obe1 hold t rwsh1 10 ns 11 reset pulse width t rpw 75 ns 12 cs to high z t rpw 10 ns 13 cs to data output valid t csov 200 ns 14 str obe2 to str obe1 setup t s2s1 0ns 15 str obe1 to str obe2 setup t s1s2 0ns 16 mr to switch open delay 50% mr to10% output t rst 300 ns 17 r/w to data output valid t rwov 150 ns 18 address to data output valid t aov 200 ns 19 r/w to high z t rwz 10 ns 20 address to high z t az 10 ns 21 str obe2 to switch status delay 50% strobe to10% output change tstrobe2(on) tstrobe2(off) t son t soff 100 100 300 300 ns ns
MT88V32 preliminary information 3-64 figure 14 - write cycle timing diagram figure 15 - read cycle timing diagram t css1 t csh1 t rpw t spw1 t ass1 t dh1 t son t rst t ds1 cs str obe1 address data switch on off mr t ash1 t s1s2 t s2s1 r/w t rwss1 t rwsh1 t spw2 str obe2 status t soff t rwz t aov t az cs address data high z r/w t csov t rwov high z data valid t csz note: str obe1 is disabled when r/w is at logic "1".

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